256 lines
8.7 KiB
C
Executable File
256 lines
8.7 KiB
C
Executable File
/************************
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*** Team Kitty, 2019 ***
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*** Sync ***
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***********************/
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/* This file combines the implementation
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of IDT and GDT, Interrupt Descriptor
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Table and Global Descriptor Table
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respectively.
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These are in the same file, because
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otherwise the GDT file would be
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roughly 10 lines long.
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This file contains the code to set up
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and configure the PIC, to configure and
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load the IDT and GDT through the processor,
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and other functions that are uniquely
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related to the above tasks. */
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#include <kernel.h>
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/*
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* The GDT gate setting function.
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* Defines where the important parts of memory are.
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*
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* @param num: GDT position ID.
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* @param base: Start of the memory block this entry is for.
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* @param limit: End of the above memory block.
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* @param access: The ring number associated with this entry.
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* @param gran: Granularity - how big the assigned chunks of memory are.
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*/
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void gdt_set_gate(int num, uint32_t base,
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uint32_t limit, uint8_t access,
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uint8_t gran) {
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/* The function is mostly shifts and masks, nothing too special. */
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/* The gdt[] array is defined in the descriptor_tables header. */
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gdt[num].low_base = (base & 0xFFFF);
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gdt[num].middle_base = (base >> 16) & 0xFF;
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gdt[num].high_base = (base >> 24) & 0xFF;
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gdt[num].low_limit = (limit & 0xFFFF);
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gdt[num].granular = ((limit >> 16) & 0x0F);
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gdt[num].granular = (gran & 0xF0);
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gdt[num].access = access;
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}
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/*
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The function that puts it all together. It sets up the pointer,
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fills it in, and tells the CPU to load the new GDT immediately.
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*/
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void gdt_install() {
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/* gp = GDT Pointer, defined in descriptor_tables header. */
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gp.limit = (sizeof(struct gdt_item) * 3) - 1;
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gp.base = (uint32_t)&gdt;
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/* The CPU requires that the first gate always be null. */
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gdt_set_gate(0, 0, 0, 0, 0);
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/* This is the Code Segment, it starts at 0 and ends at 4GB, meaning
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that it encompasses the entirety of available memory.
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This defines the code segment with exclusive execute permission,
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allowing the kernel to execute itself. */
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gdt_set_gate(1, 0, 0xFFFFFFFF, 0x9A, 0xCF);
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/* The Data Segment, the same range as the Code Segment (0 - 4GB)
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but with Read/Write permission, allowing the kernel to modify RAM. */
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gdt_set_gate(2, 0, 0xFFFFFFFF, 0x92, 0xCF);
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/* Lastly, call the external ASM function that loads the GDT into the
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processor. */
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load_gdt();
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}
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/*
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Identically to the GDT set gate function, but for the IDT array.
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* @param num: IDT access ID
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* @param base: Start of memory block
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* @param sel: Selector. I have no idea what that means.
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* @param flags: Permission levels and all that stuff.
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*/
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void idt_set_gate(unsigned char num,
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unsigned long base,
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unsigned short sel,
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unsigned char flags) {
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/* Again, it's all shifts and masks. Nothing special. */
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idt[num].base_low = base & 0xFFFF;
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idt[num].base_high = (base >> 16) & 0xFFFF;
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idt[num].selector = sel;
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idt[num].always0 = 0;
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/* Set the permission level to 3. All interrupts are from ring 3. */
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idt[num].flags = flags | 0x60;
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}
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/*
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Same as GDT_install: sets up the pointers and fills in the contents, then passes
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it on to the CPU to be loaded.
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*/
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void idt_install() {
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/* idtp is the IDT Pointer, defined in the descriptor_tables header. */
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idtp.limit = (sizeof (struct idt_entry) * 256) - 1;
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idtp.base = (uint32_t) &idt;
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memset(&idt, 0, sizeof(struct idt_entry) * 256);
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/* Manually fill in the array - these functions are defined in
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interrupts.c */
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idt_set_gate(0, (unsigned)isr0, 0x08, 0x8E);
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idt_set_gate(1, (unsigned)isr1, 0x08, 0x8E);
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idt_set_gate(2, (unsigned)isr2, 0x08, 0x8E);
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idt_set_gate(3, (unsigned)isr3, 0x08, 0x8E);
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idt_set_gate(4, (unsigned)isr4, 0x08, 0x8E);
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idt_set_gate(5, (unsigned)isr5, 0x08, 0x8E);
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idt_set_gate(6, (unsigned)isr6, 0x08, 0x8E);
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idt_set_gate(7, (unsigned)isr7, 0x08, 0x8E);
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idt_set_gate(8, (unsigned)isr8, 0x08, 0x8E);
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idt_set_gate(9, (unsigned)isr9, 0x08, 0x8E);
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idt_set_gate(10, (unsigned)isr10, 0x08, 0x8E);
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idt_set_gate(11, (unsigned)isr11, 0x08, 0x8E);
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idt_set_gate(12, (unsigned)isr12, 0x08, 0x8E);
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idt_set_gate(13, (unsigned)isr13, 0x08, 0x8E);
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idt_set_gate(14, (unsigned)isr14, 0x08, 0x8E);
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idt_set_gate(15, (unsigned)isr15, 0x08, 0x8E);
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idt_set_gate(16, (unsigned)isr16, 0x08, 0x8E);
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idt_set_gate(17, (unsigned)isr17, 0x08, 0x8E);
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idt_set_gate(18, (unsigned)isr18, 0x08, 0x8E);
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idt_set_gate(19, (unsigned)isr19, 0x08, 0x8E);
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idt_set_gate(20, (unsigned)isr20, 0x08, 0x8E);
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idt_set_gate(21, (unsigned)isr21, 0x08, 0x8E);
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idt_set_gate(22, (unsigned)isr22, 0x08, 0x8E);
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idt_set_gate(23, (unsigned)isr23, 0x08, 0x8E);
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idt_set_gate(24, (unsigned)isr24, 0x08, 0x8E);
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idt_set_gate(25, (unsigned)isr25, 0x08, 0x8E);
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idt_set_gate(26, (unsigned)isr26, 0x08, 0x8E);
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idt_set_gate(27, (unsigned)isr27, 0x08, 0x8E);
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idt_set_gate(28, (unsigned)isr28, 0x08, 0x8E);
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idt_set_gate(29, (unsigned)isr29, 0x08, 0x8E);
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idt_set_gate(30, (unsigned)isr30, 0x08, 0x8E);
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idt_set_gate(31, (unsigned)isr31, 0x08, 0x8E);
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idt_load();
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irq_install();
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}
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/* A simple wrapper that adds a function pointer to the IRQ array. */
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void irq_install_handler(int irq, void (*handler)(struct int_frame* r)) {
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irq_routines[irq] = handler;
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}
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/* A simple wrapper that unlinks a function pointer, rendering the IRQ unused. */
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void irq_uninstall_handler(int irq) {
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irq_routines[irq] = 0;
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}
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/*
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Since the PIC starts with irq values that overlap with the CPU default ISR
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lines, it's necessary to remap the PIC.
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Doing this also means that we have to completely reinitialize the PIC, which
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is why this is so long.
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*/
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void irq_remap() {
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/* 0x20 is the Master PIC,
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0xA0 is the Slave PIC. */
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outb(0x20, 0x11);
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outb(0xA0, 0x11);
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outb(0x21, 0x20);
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outb(0xA1, 0x28);
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outb(0x21, 0x04);
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outb(0xA1, 0x02);
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outb(0x21, 0x01);
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outb(0xA1, 0x01);
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outb(0x21, 0x0);
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outb(0xA1, 0x0);
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}
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/* A handler function to perform all of the required steps in one function call.
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TODO: move all Descriptor Table things to a single callable function.
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*/
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void irq_install() {
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irq_remap();
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idt_set_gate(32, (unsigned)irq0, 0x08, 0x8E);
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idt_set_gate(33, (unsigned)irq1, 0x08, 0x8E);
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idt_set_gate(34, (unsigned)irq2, 0x08, 0x8E);
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idt_set_gate(35, (unsigned)irq3, 0x08, 0x8E);
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idt_set_gate(36, (unsigned)irq4, 0x08, 0x8E);
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idt_set_gate(37, (unsigned)irq5, 0x08, 0x8E);
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idt_set_gate(38, (unsigned)irq6, 0x08, 0x8E);
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idt_set_gate(39, (unsigned)irq7, 0x08, 0x8E);
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idt_set_gate(40, (unsigned)irq8, 0x08, 0x8E);
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idt_set_gate(41, (unsigned)irq9, 0x08, 0x8E);
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idt_set_gate(42, (unsigned)irq10, 0x08, 0x8E);
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idt_set_gate(43, (unsigned)irq11, 0x08, 0x8E);
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idt_set_gate(44, (unsigned)irq12, 0x08, 0x8E);
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idt_set_gate(45, (unsigned)irq13, 0x08, 0x8E);
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idt_set_gate(46, (unsigned)irq14, 0x08, 0x8E);
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idt_set_gate(47, (unsigned)irq15, 0x08, 0x8E);
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}
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/* All of the ISR routines call this function for now.
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! This function is NOT leaf, and it might clobber the stack.
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! Be careful!
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*/
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void isr_common(struct int_frame* r, size_t exception) {
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/* We only have the capacity to handle 32 exceptions. This is a limitation of the CPU. */
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if(exception < 32) {
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/* exception_messages is an array defined in descriptor_tables.h */
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serial_print(0x3F8, exception_messages[exception]);
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serial_print(0x3F8, " Exception.\r\n");
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panic(exception_messages[exception]);
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}
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}
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/* The common handler for exceptions that throw error codes, which give us useful insight
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into what went wrong. In pure Curle style, though, we just ignore the error code. */
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void isr_error_common(struct int_frame* r, size_t exception, size_t error) {
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if(exception < 32) {
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serial_print(0x3F8, exception_messages[exception]);
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serial_printf(0x3F8, " Exception. Context given: %d\r\n", error);
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panic(exception_messages[exception]);
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}
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}
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/* Likewise, this function is common to all IRQ handlers. It calls the assigned routine,
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which was set up earlier by irq_install.*/
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void irq_common(struct int_frame* r, size_t interrupt) {
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void (*handler)(struct int_frame* r);
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serial_print(0x3F8, "[INFO] Received IRQ: " + interrupt);
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/* We set all uninitialized routines to 0, so the if(handler) check here allows us to
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safely tell whether we've actually got something for this IRQ. */
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handler = irq_routines[interrupt];
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if(handler)
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handler(r);
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/* The Slave PIC must be told it's been read in order to receive another 8+ IRQ. */
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if(interrupt > 7)
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outb(0xA0, 0x20);
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/* In either case, we tell the Master PIC it's been read to receive any IRQ. */
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outb(0x20, 0x20);
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}
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