342 lines
12 KiB
C
342 lines
12 KiB
C
#include <kernel/chroma.h>
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/************************
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*** Team Kitty, 2020 ***
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*** Chroma ***
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***********************/
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/****************************************
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* W O R K I N P R O G R E S S *
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****************************************
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*
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* This file contains functions for virtual memory management.
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*
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* Virtual Memory Management is still a work in progress.
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* The functions here are hold-offs from old versions of the software implemented here, as well as from the EFI version of Chroma, called Sync.
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*
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* There, these functions worked, but here, under BIOS, it's a lot more difficult.
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* It will take some time to get these functions working.
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*
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*/
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//__attribute__((aligned(4096))) static size_t Pagetable[512] = {0};
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#define LAST_ENTRY 0xFF8
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#define SET_ADDRESS(a,b) ((*(size_t*) (a)) = (size_t) b)
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#define KiB 1 * 1024
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#define MiB 1 * 1024 * KiB
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#define USERWRITEABLE_FLAGS(a) ((a & 0xFFFFFF00) + 0x83)
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#define PAGE_PRESENT 1
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#define PAGE_RW 2
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void InitPaging() {
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size_t* PML4 = (size_t*) 0xFFA000; // Layer 4
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size_t* PDPE_RAM = (size_t*) 0xFFE000; // Layer 3, contains map for the first 4GB of RAM
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size_t* PDE_RAM = (size_t*) 0xFFF000;
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size_t* PDPE_KERNEL = (size_t*) 0xFFB000; // Layer 3, contains map for the Kernel and everything it needs to run.
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size_t* PDE_KERNEL_FB = (size_t*) 0xFFC000; // Layer 2, contains map for the linear framebuffer.
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size_t* PT_KERNEL = (size_t*) 0xFFD000; // Layer 1, the page table for the kernel itself.
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size_t fb_ptr = (size_t) &fb;
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SET_ADDRESS(PML4, PDPE_RAM); // 3rd Layer entry for RAM
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SET_ADDRESS(PML4 + LAST_ENTRY, PDPE_KERNEL); // 3rd Layer entry for Kernel
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SET_ADDRESS(PDPE_KERNEL + LAST_ENTRY, PDE_KERNEL_FB); // 2nd Layer entry for the framebuffer
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// Set the 480th entry (PDE_KERNEL_FB + (480 * 8))
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// To the framebuffer + flags
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SET_ADDRESS(PDE_KERNEL_FB + 3840, USERWRITEABLE_FLAGS(fb_ptr));
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// In 4 byte increments, we're gonna map 3840 (the framebuffer)
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// Up to (4096 - 8) in the PDE_KERNEL_FB with 2MB paging.
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size_t MappingIterations = 1;
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for(size_t i = 3844; i < 4088; i += 4) {
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SET_ADDRESS(PDE_KERNEL_FB + i, USERWRITEABLE_FLAGS(fb_ptr) + (MappingIterations * (2 * MiB)));
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MappingIterations++;
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}
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// Now we map the last entry of PDE_KERNEL_FB to our Page Table
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SET_ADDRESS(PDE_KERNEL_FB + LAST_ENTRY, PT_KERNEL);
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// Mapping the kernel into the page tables....
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SET_ADDRESS(PT_KERNEL, 0xFF8001); // bootldr, bootinfo
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SET_ADDRESS(PT_KERNEL + 8, 0xFF9001); // environment
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// Map the kernel itself
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SET_ADDRESS(PT_KERNEL + 16, KernelAddr + 1);
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// Iterate through the pages, identity mapping each one
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MappingIterations = 1;
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size_t MappingOffset = 0x14;
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for(size_t i = 0; i < ((KernelEnd - KernelAddr) >> 12); i++) {
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// Page Table + (0x10 increasing by 0x04 each time) = x * 4KiB
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SET_ADDRESS(PT_KERNEL + MappingOffset, (MappingIterations * (4 * KiB)));
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MappingOffset += 4;
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MappingIterations++;
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}
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// Now we need to map the core stacks. Top-down, from 0xDFF8
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// There's always at least one core, so we do that one fixed.
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// TODO: Account for 0-core CPUs
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SET_ADDRESS(PT_KERNEL + LAST_ENTRY, 0xF14003);
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MappingIterations = 1;
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// For every core:
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for(size_t i = 0; i < (bootldr.numcores + 3U) >> 2; i++) {
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// PT_KERNEL[512 - (iterations + 1)] = 0x14003 + (iterations * page-width)
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SET_ADDRESS(PT_KERNEL + LAST_ENTRY - (MappingIterations * 8), 0xF14003 + (4096 * MappingIterations));
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MappingIterations++;
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}
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SET_ADDRESS(PDPE_RAM, PDE_RAM + PAGE_PRESENT + PAGE_RW);
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SET_ADDRESS(PDPE_RAM + 8, 0xF10000 + PAGE_PRESENT + PAGE_RW);
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SET_ADDRESS(PDPE_RAM + 16, 0xF11000 + PAGE_PRESENT + PAGE_RW);
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SET_ADDRESS(PDPE_RAM + 24, 0xF12000 + PAGE_PRESENT + PAGE_RW);
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// Identity map 4GB of ram
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// Each page table can only hold 512 entries, but we
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// just set up 4 of them - overflowing PDE_RAM (0xF000)
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// will take us into 0x10000, into 0x11000, into 0x120000.
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for(size_t i = 0; i < 512 * 4/*GB*/; i++) {
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// add PDE_RAM, 4
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// mov eax, 0x83
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// add eax, 2*1024*1024
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SET_ADDRESS(PDE_RAM + (i * 4), USERWRITEABLE_FLAGS(i * (2 * MiB)));
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}
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// Map first 2MB of memory
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SET_ADDRESS(PDE_RAM, 0xF13000 + PAGE_PRESENT + PAGE_RW);
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for(size_t i = 0; i < 512; i++) {
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SET_ADDRESS(0xF13000 + i * 4, i * (4 * KiB) + PAGE_PRESENT + PAGE_RW);
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}
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// 0xA000 should now contain our memory map.
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}
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void InitPagingOldImpl() {
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// Disable paging so that we can work with the pagetable
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//size_t registerTemp = ReadControlRegister(0);
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//UNSET_PGBIT(registerTemp);
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//WriteControlRegister(0, registerTemp);
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// Clear space for our pagetable
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size_t PagetableDest = 0x1000;
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memset((char*)PagetableDest, 0, 4096);
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// Start setting pagetable indexes
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*((size_t*)PagetableDest) = 0x2003; // PDP at 0x2000, present & r/w
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*((size_t*)PagetableDest + 0x1000) = 0x3003; // PDT at 0x3000, present & r/w
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*((size_t*)PagetableDest + 0x2000) = 0x4003; // PT at 0x4000, present & r/w
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size_t value = 0x3;
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size_t offset = 8;
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for(size_t i = 0; i < 512; i++) { // 512 iterations (entries into the page table)
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*((size_t*) PagetableDest + offset) = value; // We're setting 512 bytes with x003
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// (identity mapping the first 4 megabytes of memory)
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// (mapping the page table to itself)
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value += 4096; // Point to start of next page
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offset += 8; // + 8 bytes (next entry in list)
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}
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// Enable PAE paging
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size_t reg = ReadControlRegister(4);
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SET_PAEBIT(reg);
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WriteControlRegister(4, reg);
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WriteControlRegister(3, PagetableDest);
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}
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/* size_t registerTemp = ReadControlRegister(4);
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if(registerTemp & (1 << 7)) {
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TOGGLE_PGEBIT(registerTemp);
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WriteControlRegister(4, registerTemp);
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}
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if(registerTemp & (1 << 7))
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WriteControlRegister(4, registerTemp ^ (1 << 7));
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size_t CPUIDReturn;
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asm volatile("cpuid" : "=d" (CPUIDReturn) : "a" (0x80000001) : "%rbx", "%rcx");
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if(CPUIDReturn & (1 << 26)) {
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SerialPrintf("System supports 1GB pages.\r\n");
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if(registerTemp & (1 << 12)) {
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SerialPrintf("PML5 paging available - using that instead.\r\n");
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if(MemorySize > (1ULL << 57))
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SerialPrintf("System has over 128Petabytes of RAM. Please consider upgrading the OS on your supercomputer.\r\n");
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size_t MaxPML5 = 1;
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size_t MaxPML4 = 1;
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size_t MaxPDP = 512;
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size_t LastPML4Entry = 512;
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size_t LastPDPEntry = 512;
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size_t MemorySearchDepth = MemorySize;
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while(MemorySearchDepth > (256ULL << 30)) {
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MaxPML5++;
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MemorySearchDepth -= (256ULL << 30);
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}
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if(MaxPML5 > 512)
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MaxPML5 = 512;
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if(MemorySearchDepth) {
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LastPDPEntry = ( (MemorySearchDepth + ((1 << 30) - 1)) & (~0ULL << 30)) >> 30;
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if(MaxPML5 > 512)
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MaxPML5 = 512;
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}
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size_t PML4Size = PAGETABLE_SIZE * MaxPML5;
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size_t PDPSize = PML4Size * MaxPML4;
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size_t PML4Base = AllocatePagetable(PML4Size + PDPSize);
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size_t PDPBase = PML4Base + PML4Size;
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for(size_t PML5Entry = 0; PML5Entry < MaxPML5; PML5Entry++) {
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Pagetable[PML5Entry] = PML4Base + (PML5Entry << 12);
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if(PML5Entry == (MaxPML5 - 1))
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MaxPML4 = LastPML4Entry;
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for(size_t PML4Entry = 0; PML4Entry < MaxPML4; PML4Entry++) {
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((size_t*) Pagetable[PML5Entry])[PML4Entry] = PDPBase + (((PML5Entry << 9) + PML5Entry) << 12);
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if( (PML5Entry == (MaxPML5 - 1)) && (PML4Entry == (MaxPML4 -1)) )
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MaxPDP = LastPDPEntry;
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for(size_t PDPEntry = 0; PDPEntry < MaxPDP; PDPEntry++) {
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((size_t* ) ((size_t* ) Pagetable[PML5Entry])[PML4Entry])[PDPEntry] = ( ((PML5Entry << 18) + (PML4Entry << 9) + PDPEntry) << 30) | (0x83);
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}
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((size_t* ) Pagetable[PML5Entry])[PML4Entry] |= 0x3;
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}
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Pagetable[PML5Entry] |= 0x3;
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}
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} else {
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SerialPrintf("PML4 available - using that instead.\r\n");
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size_t MemorySearchDepth = MemorySize;
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if(MemorySearchDepth > (1ULL << 48))
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SerialPrintf("RAM limited to 256TB.\r\n");
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size_t MaxPML4 = 1;
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size_t MaxPDP = 512;
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size_t LastPDPEntry = 512;
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while(MemorySearchDepth > (512ULL << 30)) {
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MaxPML4++;
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MemorySearchDepth -= (512ULL << 30);
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}
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if(MaxPML4 > 512)
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MaxPML4 = 512;
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if(MemorySearchDepth) {
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LastPDPEntry = ( (MemorySearchDepth + ((1 << 30) - 1)) & (~0ULL << 30)) >> 30;
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if(LastPDPEntry > 512)
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LastPDPEntry = 512;
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}
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size_t PDPSize = PAGETABLE_SIZE * MaxPML4;
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size_t PDPBase = AllocatePagetable(PDPSize);
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for(size_t PML4Entry = 0; PML4Entry < MaxPML4; PML4Entry++) {
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Pagetable[PML4Entry] = PDPBase + (PML4Entry << 12);
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if(PML4Entry == (MaxPML4 - 1)) {
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MaxPDP = LastPDPEntry;
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}
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for(size_t PDPEntry = 0; PDPEntry < MaxPDP; PDPEntry++) {
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((size_t* ) Pagetable[PML4Entry])[PDPEntry] = (((PML4Entry << 9) + PDPEntry) << 30) | 0x83;
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}
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Pagetable[PML4Entry] |= 0x3;
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}
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}
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} else {
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SerialPrintf("System does not support 1GB pages - using 2MiB paging instead.\r\n");
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size_t MemorySearchDepth = MemorySize;
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if(MemorySearchDepth > (1ULL << 48)) {
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SerialPrintf("Usable RAM is limited to 256TB, and the page table alone will use 1GB of space in memory.\r\n");
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}
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size_t MaxPML4 = 1, MaxPDP = 512, MaxPD = 512, LastPDPEntry = 1;
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while(MemorySearchDepth > (512ULL << 30)) {
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MaxPML4++;
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MemorySearchDepth -= (512ULL << 30);
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}
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if(MaxPML4 > 512)
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MaxPML4 = 512;
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if(MemorySearchDepth) {
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LastPDPEntry = ((MemorySearchDepth + ((1 << 30) - 1)) & (~0ULL << 30)) >> 30;
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if(LastPDPEntry > 512)
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LastPDPEntry = 512;
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}
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size_t PDPSize = PAGETABLE_SIZE * MaxPML4;
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size_t PDSize = PDPSize * MaxPDP;
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size_t PDPBase = AllocatePagetable(PDPSize + PDSize);
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size_t PDBase = PDPBase + PDSize;
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for(size_t PML4Entry = 0; PML4Entry < MaxPML4; PML4Entry++) {
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Pagetable[PML4Entry] = PDBase + (PML4Entry << 12);
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if(PML4Entry == (MaxPML4 - 1)) {
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MaxPDP = LastPDPEntry;
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}
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for(size_t PDPEntry = 0; PDPEntry < MaxPDP; PDPEntry++) {
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( (size_t* ) Pagetable[PML4Entry])[PDPEntry] = PDBase + (((PML4Entry << 9) + PDPEntry) << 12);
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for(size_t PDEntry = 0; PDEntry < MaxPD; PDEntry++) {
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( (size_t* ) ((size_t*) Pagetable[PML4Entry])[PDPEntry])[PDEntry] = (( (PML4Entry << 18) + (PDPEntry << 9) + PDPEntry) << 21) | 0x83;
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}
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( (size_t* ) Pagetable[PML4Entry])[PDPEntry] |= 0x3;
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}
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Pagetable[PML4Entry] |= 0x3;
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}
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}
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WriteControlRegister(3, Pagetable);
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registerTemp = ReadControlRegister(4);
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if(!(registerTemp & (1 << 7))) {
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TOGGLE_PGEBIT(registerTemp);
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WriteControlRegister(4, registerTemp);
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}*/ |