183 lines
9.1 KiB
C
183 lines
9.1 KiB
C
#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stddef.h>
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/************************
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*** Team Kitty, 2020 ***
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*** Chroma ***
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***********************/
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/* This file contains all of the structures and definitions
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* required to compatibly access the PCI bus,
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* as well as set up new PCI devices, PCI bridges, and manipulate
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* the connections of PCI lanes.
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*/
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#define PCI_CONFIG_ADDRESS 0xCF8
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#define PCI_CONFIG_DATA 0xCFC
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const char* PCIGetDeviceName_Subclass(uint8_t DeviceClass, uint8_t Subclass, uint8_t ProgrammableInterface);
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const char* PCIGetClassName(uint8_t DeviceClass);
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void PCIEnumerate();
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uint32_t PCIReadConfig(uint8_t bus, uint8_t slot, uint8_t function, uint8_t offset);
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typedef struct __attribute__((packed)) {
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uint8_t IOMapped : 1; // Device can respond to I/O access
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uint8_t MMIOMapped : 1; // Device can respond to memory access (device is MMIO mapped)
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uint8_t IsBusMaster : 1; // Device is Bus Master; can generate PCI addresses
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uint8_t MonitorSpecialCycle : 1; // Device can monitor Special Cycle
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uint8_t AllowMemWriteInvalidate : 1; // Device can generate Memory Write And Invalidate commands; else Memory Write must be used
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uint8_t SnoopVGA : 1; // Device snoops the VGA palette on write; else is treated like a normal access
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uint8_t RespondsParityError : 1; // Device responds to Parity Errors by setting PERR#; else will set pci_status#ParityError and continue.
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uint8_t _reserved : 1; // Hardwired to 0
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uint8_t SystemErr : 1; // Enable SERR# driver; System ERRor
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uint8_t FastBack2Back : 1; // Device is allowed to generate fast back-to-back transactions to other agents.
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uint8_t DisableInterrupt : 1; // Disable assertion of INTx# signal; else enable.
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} pci_command_t;
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typedef struct __attribute__((packed)) {
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uint8_t _reserved : 3; // 3 bits hardwired to 0
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uint8_t InterruptActive : 1; // State of device's INTx# signal. If pci_command#DisableInterrupt is 0 and this is 1, the signal will be asserted.
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uint8_t Capabilities : 1; // If set, device will implement New Capabilities list at 0x34 offset.
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uint8_t Mhz66Capable : 1; // Device can run at 66MHz. Else, device will run at 33MHz.
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uint8_t _reserved1 : 1; // Reserved as of 3.0, Used in 2.1 as "Supports User Definable Features"
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uint8_t FastBack2Back : 1; // Device is allowed to accept fast back-to-back transactions from other agents.
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uint8_t MasterParityError : 1; // Only set when PERR# is asserted by the Bus Master while pci_command#RespondsParityError is set.
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uint8_t DEVSELTiming : 2; // Read-Only; represents the slowest time a device will assert DEVSEL#. 00 = fast, 01 = medium, 11 = slow.
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uint8_t TargetAborted : 1; // Target device terminated transaction via Target-Abort
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uint8_t ReceivedTargetAbort : 1; // Master's connection was terminated by Target-Abort
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uint8_t ReceivedMasterAbort : 1; // Master's connection was terminated by Master-Abort
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uint8_t SystemAssertedError : 1; // Device asserted SERR#
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uint8_t ParityError : 1; // Device detected parity error. Parity error may not be handled.
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} pci_status_t;
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typedef struct __attribute__((packed)) {
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uint16_t VendorID; // 16 bit Vendor ID allocated by PCI-SIG. 0xFFFF is invalid.
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uint16_t DeviceID; // 16 bit Device ID allocated by the vendor.
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pci_command_t Command; // 16 bit PCI_COMMAND register.
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pci_status_t Status; // 16 bit PCI_STATUS register.
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uint8_t RevisionID; // 8 bit register, revision identifier specified by vendor.
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uint8_t ProgrammingInterface; // 8 bit register, identifies any programming interface the device may have.
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uint8_t Subclass; // 8 bit Subclass code; identifies the specific function of the device
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uint8_t ClassCode; // 8 bit Class Code; identifies the function of the device
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uint8_t CacheLine; // 8 bit; specifies system cache line size in 32-bit blocks. Devices can limit this. Unsupported values are treated as 0.
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uint8_t LatencyTimer; // 8 bit; specifies latency timer in (bus clock) units.
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uint8_t HeaderType; // 8 bit; identifies the layout of the header and the type of device; 00 = device, 01 = pci-pci bridge, 11 = CardBus bridge. Multi-function defined by bit 7.
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uint8_t BuiltInSelfTest; // 8 bit; status and control of a device's built-in self-test (BIST)
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} pci_header_common_t;
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typedef struct __attribute__((packed)) {
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// pci_header_common_t first, then..
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uint32_t BARs[6]; // 6 x 32 bit Base Address Registers (BARs)
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uint32_t CISPtr; // Points to Card Information Structure for PCI devices that share silicon with CardBus
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uint16_t SubsysVendor;
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uint16_t SubsysID;
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uint32_t ExpansionBAR; // Points to the base of an Expansion ROM.
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uint8_t Capabilities; // The pointer generated by pci_status#capabilities_list
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uint8_t _reserved[3]; // 24 bit reserved at top end of register.
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uint32_t _reserved2;
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uint8_t InterruptPin; // Specifies the PIC pin that INTx# is connected to. Can be 0-15 because x86 PICs have 16 IRQs. 0xFF is no connection.
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uint8_t InterruptActive; // Specifies the interrupt pin the device uses. 0x1 is INTA#, 0x2 is INTB#, 0x3 is INTC#, 0x4 is INTD#, 0x0 is no interrupt.
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uint8_t MinimumTimeshare; // Specifies the length of the burst period, in quarter-microsecond units
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uint8_t MaxmimumTimeshare; // Specifies how often the device accesses the PCI bus - in quarter-microseconds
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} pci_header_device_t;
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typedef struct __attribute__((packed)) {
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// pci_header_common_t first
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uint32_t BARs[2];
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uint8_t PrimaryBus; // Primary Bus Number.
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uint8_t SecondaryBus; // Secondary Bus Number.
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uint8_t SubordinateBus; // Subordinate Bus Number.
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uint8_t LatencyTimer; // Secondary Latency Timer.
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uint8_t IOBaseLow; // IO Base is 24 bits. This is lower 8.
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uint8_t IOLimitLow; // IO Limit is 24 bits. This is lower 8.
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pci_status_t SecondaryStatus; // Secondary Status.
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uint16_t MemoryBase;
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uint16_t MemoryLimit;
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uint16_t PrefetchBaseLow; // Prefetchable Memory Base is 48 bits. This is lower 16.
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uint16_t PrefetchLimitLow; // Prefetchable Memory Limit is 48 bits. This is lower 16.
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uint32_t PrefetchBaseHigh; // Prefetchable Memory Base is 48 bits. This is upper 32.
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uint32_t PrefetchLimitHigh; // Prefetchable Memory Limit is 48 bits. This is upper 32.
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uint16_t IOBaseHigh; // IO Base is 24 bits. This is upper 16.
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uint16_t IOLimitHigh; // IO Limit is 24 bits. This is upper 16.
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uint8_t Capabilities; // Pointer generated by pci_status#capabilities_list
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uint8_t _reserved[3]; // 24 reserved bits.
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uint32_t ExpansionBAR; // Base of Expansion ROM.
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uint8_t InterruptPin; // Specifies the PIC pin that INTx# is connected to. Can be 0-15 because x86 PICs have 16 IRQs. 0xFF is no connection.
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uint8_t InterruptActive; // Specifies the interrupt pin the device uses. 0x1 is INTA#, 0x2 is INTB#, 0x3 is INTC#, 0x4 is INTD#, 0x0 is no interrupt.
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uint16_t BridgeControl;
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} pci_header_bridge_t;
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typedef struct {
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uint16_t segment;
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uint8_t bus;
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uint8_t slot;
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uint8_t function;
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} pci_address_t;
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typedef struct {
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uint8_t Present : 1;
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uint8_t MMIO : 1;
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union {
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size_t Address;
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uint16_t Port;
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};
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size_t Length;
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} pci_bar_t;
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typedef struct pci_device {
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struct pci_dev* Parent; // Parent of the device (for PCI hubs / splitters)
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uint16_t DeviceID;
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uint16_t VendorID;
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uint8_t DeviceClass;
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uint8_t Subclass;
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uint8_t ProgrammableInterface;
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pci_address_t address;
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pci_bar_t BARs[6];
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int IRQ; // The IRQ of the device if already handled
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// The headers!
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volatile pci_header_common_t* Header;
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union { // The device can only be one of these at a time, but they both form part of the config space.
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volatile pci_header_bridge_t* bridge;
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volatile pci_header_device_t* device;
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};
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struct pci_dev** Children; // If this device is a hub, it has children...
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// acpi_node_t acpi;
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} pci_device_t;
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typedef struct {
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pci_address_t key;
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pci_device_t* value;
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} pci_entry_t;
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extern pci_device_t** pci_root_devices;
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extern pci_entry_t* pci_map;
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#ifdef __cplusplus
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}
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#endif |