From 63a5bfa4d6d48b9dbf936b4b59b3a23082ec9d4c Mon Sep 17 00:00:00 2001
From: Curle <curle@gemwire.uk>
Date: Mon, 9 Nov 2020 18:43:06 +0000
Subject: [PATCH] Flailing with Invalid Opcode..

---
 chroma/inc/kernel/system/io.h |  2 +-
 chroma/system/cpu.c           | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/chroma/inc/kernel/system/io.h b/chroma/inc/kernel/system/io.h
index 72af83c..fccd498 100644
--- a/chroma/inc/kernel/system/io.h
+++ b/chroma/inc/kernel/system/io.h
@@ -55,7 +55,7 @@ uint32_t    WriteMXCSR(uint32_t Data);
 size_t      ReadControlRegister(int CRX);
 size_t      WriteControlRegister(int CRX, size_t Data);
 
-size_t      ReadExtendedControlRegister(size_t XCRX);
+//size_t      ReadExtendedControlRegister(size_t XCRX);
 size_t      WriteExtendedControlRegister(size_t XCRX, size_t Data);
 
 void        InvalidatePage(size_t Page);
diff --git a/chroma/system/cpu.c b/chroma/system/cpu.c
index dc02170..545b24d 100644
--- a/chroma/system/cpu.c
+++ b/chroma/system/cpu.c
@@ -65,13 +65,13 @@ void PrepareCPU() {
     SetupInitialGDT();
     SetupIDT();
 
-    SetupExtensions();
+    //SetupExtensions();
 
     InitInterrupts();
 
 }
 
-void SetupExtensions() {
+/*void SetupExtensions() {
 
     // Enable SSE
     size_t CR0 = ReadControlRegister(0);
@@ -97,14 +97,14 @@ void SetupExtensions() {
     CR0 |= (1 << 1);
     CR0 |= (1 << 2);
 
-    /*CR0 |= (1 << 5);
+    CR0 |= (1 << 5);
     CR0 |= (1 << 6);
-    CR0 |= (1 << 7);*/
+    CR0 |= (1 << 7);
 
     SerialPrintf("About to write xcr0: %x\n", CR0);
     WriteExtendedControlRegister(0, CR0);
 }
-
+*/
 
 void SetupInitialGDT() {
     DESC_TBL GDTData = {0};